Frequency synthesisers are an integral part of any modern communications system, especially any coherent system dependent upon a steady phase difference between each element in the communication network.
Advancing technology has made possible the use of adaptive beam steering using multiple antennas to provide a focused beam between transmitter and receiver systems, allowing the dual benefits of increased cell capacity with increased rejection of interfering signals. The ability to adjust the output phase of the frequency under digital base-band control is particularly useful as it can reduce the component count used in a transmitter system. Similarly a system which can accurately provide a phase modulated radio frequency signal offers the potential for higher levels of component integration.
Reference is made to FIG. 1, which shows a known synthesiser generally designated by reference numeral 10.
The synthesiser 10 comprises a phase detector 2, a low-pass filter 4, voltage controlled oscillator (VCO) 6, a divider 8, and an optional integer “R” divider 12. A signal having a required output frequency is generated at the output of the VOC 6.
Essentially there are two variants to this type of synthesiser, employing either fixed integer dividers or modulated dividers, by a suitably adjusted data stream, which constantly adjusts the integer divider value in the divider 8. Modulated dividers are also known as fractional-N dividers. The parasitic modulation of the divider output signal is itself modulated by this modulated data stream to ensure the remainder of the phase locked loop can remove this parasitic modulation, whilst preserving the advantages it offers.
Both types of phase locked loops use a phase frequency detector 2, which is commonly a digital element, to compare a fed back voltage controlled oscillator output with an incoming reference signal, to which the system is phase locked. The output of the phase frequency detector 2 can be a series of either current or voltage pulses, which are filtered by the loop filter 4 to give a small error voltage. This small error voltage complements the voltage pedestal at the output of the loop filter, ensuring the VCO remains phase locked. The error voltage is the correction voltage supplied to the VCO, to suppress the excess phase noise of this device to levels determined by the phase locked loop dynamic characteristics. The VCO is the device controlled by this negative feed back closed loop system. To provide a frequency translation back to the phase frequency detector 2, for comparison with the reference signal, the series divider circuit is used. If fractional-n dividers are used, as shown in FIG. 1, their mean division value can be adjusted to give an effective multiplication of the reference signal, hence allowing the phase locked system to change to different frequencies with respect to the reference signal.
Digital dividers have the net effect of raising the phase noise of the system because their dividing action in the feed back path of the system translates to a multiplication of PFD related noise in the through transfer characteristic of the phase locked loop.
Arrangements using digital dividers in their feed-back path offer limited noise performance preventing their simple implementation in new, more demanding, communication system applications.
Single loop fractional-N techniques, described earlier, have been adapted to improve on divider limitations by raising the sampling frequency seen at the digital phase frequency detector input to reduce these division values. However, a point is reached where the sampling frequency approaches half the synthesiser's output frequency (for a minimum division value of 2). Beyond this point only another 3 dB of improvement might be possible, although this still does not guarantee that the resulting in-band phase noise becomes acceptable.
Also known is the use of phase locked loops employing a mixer as a frequency translation element, in order to improve the in-band phase noise using a combination of analogue phase locked loops and direct digital synthesisers. In an alternative PLL arrangement, a mixer arrangement is used in place of the divider 8. When mixers are used, additional signal sources are required to provide this frequency translation. Mixers do not raise the in-band phase noise levels, because their action is to subtract two signals in the feed back path, giving no change in phase at the mixer output, and hence no adverse effect to a system which tracks only phase. A phase locked loop using a mixer has a minimal multiplication of any spurious energy injected into the reference input.
The direct digital synthesisers provide the necessary frequency interpolation required for attaining the specified frequency steps at the phase locked loop output. Reference is made to the Qualcom application note AN2334-4, (1990) and U.S. Pat. Nos. 4,965,533, and 5,184,093 on the subject.
Alternatively the direct digital synthesiser is applied to the phase frequency detector input, with a consequent spurious degradation seen at the phase locked loop output.
A phase locked loop possesses a typical transfer characteristic of a band-pass system. This band-pass is filter characteristic is centred about the output VCO's signal, which at high frequencies (given the low loop bandwidths of the phase locked loop) represents a very high “Q” factor that cannot be achieved any other way.
The alternative to analogue phase locked loops, as described herein above, are direct digital synthesisers. Direct digital synthesisers are not phase locked systems, as they do not possess a feedback path between their output and inputs. They are capable of open loop operation because their all-digital nature guarantees repeatable outputs under all conditions. They do not suffer from the vagrancies of analogue systems. The basic concept of direct digital synthesisers remains unchanged from the original paper presenting the idea given in 1971. As shown in FIG. 2, a direct digital synthesiser 20 is built up of three components; a digital (phase) accumulator 14, a sine (or cosine) look-up table 16, and a digital to analogue converter (DAC) 18. External to the direct digital synthesiser 20 is an analogue low pass or band pass filter 22. A reference clock 24 clocks the digital accumulator 14 and the DAC 18.
The purpose of the digital accumulator 14 is to digitally integrate the digital input word provided on an input thereto, resulting in a ramp output at the required frequency. This defines the digital input word as a phase value equivalent to the phase difference over one accumulator clock period to give the required output frequency. Every time the accumulator overflows the “carry out” bit is ignored and the accumulator output re-starts it's integration sequence, giving an output word pattern resembling a ramp. The length of the digital accumulator 14 determines the phase resolution available for each accumulator clock cycle and hence the accuracy of the output frequency. Using this concept of phase increments, the required digital input word for a given output frequency can be calculated using the expression:
      Input    ⁢                  ⁢    Accumulator    ⁢                  ⁢    Word    =                    F        Required            ×              2                  Accumulator          ⁢                                          ⁢          Length                            F              Accumulator        ⁢                                  ⁢        Clock            
In a practical system the length of the accumulator data word exceeds the resolution of the following sine look up table, therefore only the “P” most significant bits are fed into the sine look up table. The value of “P” depends upon the combined width of the sine look up table and any compression circuitry used to mirror and invert the output of the sine look-up table output. It is the function of the sine look-up table 16 to convert the truncated accumulator equivalent phase value to a digital equivalent amplitude value, using a sine or cosine transfer characteristic. This digital amplitude is converted into an analogue signal level using a digital to analogue converter 18 clocked at the same frequency as the digital accumulator 14. In some direct digital synthesiser designs additional pipelining circuitry may be added to overcome circuit settling times allowing higher frequencies of operation. There is no effect on the quality of the output signal, with such pipelining only a slight phase delay is incurred between a change in digital input to analogue output.
Direct digital synthesisers are comprised of all digital elements making them suitable for integration into a chip. However one major performance limitation is the digital-to-analogue converter at the output. This digital-to-analogue converter generates problems; reducing the spurious free dynamic range and raising the noise floor. To minimise these effects caused by sampling and aliasing during the digital-to-analogue converter operation, the passive reconstruction filter 22 is normally used to “clean-up” the signal before it is used in the remainder of the system it is employed to drive.
Direct digital synthesisers cannot operate at the required local oscillator frequencies of contemporary mobile communication systems with the necessary noise and spurious performance. Therefore in current known solutions direct digital synthesisers are combined with analogue or digital phase locked loop techniques, to perform the necessary up-conversion of their lower frequency signals.
As described hereinabove, any phase locked loop employing a digital divider in its feedback path possesses gain. Therefore any small direct digital synthesiser related spurious products would be subject to this gain, usually raising their level to unacceptable levels. Analogue loops using only a mixer in the feedback path have no such gain, giving a unity translation of input DDS spurious levels.
It is an aim of the present invention to provide a solution which overcomes the above-stated problems.